This invention relates to a phase locked loop (PLL) circuit, and more particularly to a PLL circuit in which an intermediate frequency signal can be stably generated during demodulation of a carrier-suppressed double-sideband signal.
In a prior art PLL device such as that disclosed in Japanese Unexamined Patent Publication No. 197944/83, a carrier for coherent detection purpose can be recovered even in a transmission system where a large variation of the carrier frequency tends to occur. Further, in a PLL device disclosed in Japanese Unexamined Patent Publication No. 136160/83, the synchronous detection frequency and phase are controlled to follow up the frequency and phase of an input signal so as to prevent undesirable degradation of the error rate of a demodulated signal. However, in a prior art PLL circuit incorporated in, for example, a heterodyne receiver, a band-pass filter permitting passage of a fixed intermediate frequency is provided in spite of the fact that the intermediate frequency tends to drift due to the tendency of occurrence of a drift of the characteristic of a local oscillator. Thus, an excess or shortage of demodulated sidebands attributable to the provision of the frequency-fixed band-pass filter has not utterly been taken into consideration.